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1) An Antifuse programming technology is predominantly associated with _____. a. SPLDs b. FPGAs c. CPLDs d. All of the above
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2) In fusible link technologies, the undesired fuses are removed by the pulse application of _____voltage & current to device input. a. Low b. Moderate c. High d. All of the above
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3) Which programming technology/ies is/are predominantly associated with SPLDs and CPLDs? a. EPROM b. EEPROM c. FLASH d. All of the above
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4) Before the commencement of design, the clocking strategy determine/s __________ a. Number of clock signals necessary for routing throughout the chip b. Number of transistors used per storage requirement c. Power dissipated by chip & the size of chip d. All of the above
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5) Which method/s of physical clocking is/are a /the recursive structure where the memory elements are grouped together to make the use of nearby or same distribution points? a. H tree b. Balanced tree clock network c. Both a and b d. None of the above
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6) Increase in the physical distance of H-tree _________the skew rate. a. Increases b. Stabilizes c. Decreases d. All of the above
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7) Which type of MOSFET exhibits no current at zero gate voltage? a. Depletion MOSFET b. Enhancement MOSFET c. Both a and b d. None of the above
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8) In enhancement MOSFET, the magnitude of output current __________ due to an increase in the magnitude of gate potentials. a. Increases b. Remains constant c. Decreases d. None of the above
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9) In DIBL, which among the following is/are regarded as the source/s of leakage? a. Subthreshold conduction b. Gate leakage c. Junction leakage d. All of the above
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10) Which among the following can be regarded as an/the application/s of MOS switch in an IC design? a. Multiplexing & Modulation b. Transmission gate in digital circuits c. Simulation of a resistor d. All of the above
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