1) What is the divisional range of program memory for internal and external memory portions respectively when enable access pin is held high (unity)? a. 0000H - 0FFFH & 1000H - FFFFH b. 0000H - 1000H & 0FFFH - FFFFH c. 0001H - 0FFFH & 01FFH - FFFFH d. None of the above
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2) Consider the following statements. Which of them is/are correct in case of program execution related to program memory?
a. External Program memory execution takes place from 1000H through 0FFFFH only when the status of EA pin is high (1) b. External Program memory execution takes place from 0000H through 0FFFH only when the status of EA pin is low (0) c. Internal Program execution occurs from 0000H through 0FFFH only when the status of EA pin is held low (0) d. Internal program memory exe a. A & C b. B & D c. A & B d. Only A
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3) How does the processor respond to an occurrence of the interrupt? a. By Interrupt Service Subroutine b. By Interrupt Status Subroutine c. By Interrupt Structure Subroutine d. By Interrupt System Subroutine
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4) Which address/location in the program memory is supposed to get occupied when CPU jump and execute instantaneously during the occurrence of an interrupt? a. Scalar b. Vector c. Register d. All of the above
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5) Which location specify the storage/loading of vector address during the interrupt generation? a. Stack Pointer b. Program Counter c. Data Pointer d. All of the above
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6) Match the following :
a. ISS ----------------------------- 1. Monitors the status of interrupt pin b. IER ----------------------------- 2. Allows the termination of ISS c. RETI --------------------------- 3. MCS-51 Interrupts Initialization d. INTO -------------------------- 4. Occurrence of high to low transition level a. A-1, B-2, C-3, D-4 b. A-3, B-2, C-4, D-1 c. A-1, B-3, C-2, D-4 d. A-4, B-3, C-2, D-1
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7) What kind of triggering configuration of external interrupt intimate the signal to stay low until the generation of subsequent interrupt? a. Edge-Triggering b. Level Triggering c. Both a & b d. None of the above
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8) What is the counting rate of a machine cycle in correlation to the oscillator frequency for timers? a. 1 / 10 b. 1 / 12 c. 1 / 15 d. 1 / 20
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9) Which special function register play a vital role in the timer/counter mode selection process by allocating the bits in it? a. TMOD b. TCON c. SCON d. PCON
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10) How many machine cycle/s is/are executed by the counters in 8051 in order to detect '1' to '0' transition at the external pin? a. One b. Two c. Four d. Eight
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11) Which bit must be set in TCON register in order to start the 'Timer 0' while operating in 'Mode 0'? a. TR0 b. TF0 c. IT0 d. IE0
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12) Which timer mode exhibit the necessity to generate the interrupt by setting EA bit in IE enhancing the program counter to jump to another vector location? a. Mode 0 b. Mode 1 c. Mode 2 d. Mode 3
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13) What is the maximum delay generated by the 12 MHz clock frequency in accordance to an auto-reload mode (Mode 2) operation of the timer? a. 125 μs b. 250 μs c. 256 μs d. 1200 μs
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14) Which among the below mentioned sequence of program instructions represent the correct chronological order for the generation of 2kHz square wave frequency?
1. MOV TMOD, 0000 0010 B 2. MOV TL0, # 06H 3. MOV TH0, # 06H 4. SETB TR0 5. CPL p1.0 6. ORG 0000H a. 6, 5, 2, 4, 1, 3 b. 6, 1, 3, 2, 4, 5 c. 6, 5, 4, 3, 2, 1 d. 6, 2, 4, 5, 1, 3
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15) Why is it not necessary to specify the baud rate to be equal to the number of bits per second? a. Because each bit is preceded by a start bit & followed by one stop bit b. Because each byte is preceded by a start byte & followed by one stop byte c. Because each byte is preceded by a start bit & followed by one stop bit d. Because each bit is preceded by a start byte &followed by one stop byte
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16) Which factor/s is/are supposed to have the equal values at both phases of transmission and reception levels with an intimation of error-free serial communication? a. Baud Rate b. Number of data bits & stop bits c. Status of Parity bits d. All of the above
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17) Which bits exhibit and signify the termination phase of the character transmission and reception in SCON special function register? a. Control bits b. Status bits c. Both a & b d. None of the above
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18) Which two bits are supposed to be analyzed/tested for unity value (1) in SCON for the reception of byte in mode 1 serial communication? a. RI & TI b. REN & RB8 c. RI & REN d. TI & RB8
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19) What is the bit transmitting or receiving capability of mode 1 in serial communication? a. 8 bits b. 10 bits c. 11 bits d. 12 bits
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20) Which pin in the shift register mode (Mode 0) of serial communication allow the data transmission as well as reception? a. TXD b. RXD c. RB8 d. REN
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