1) What happens when the supply voltage falls below 4V during the power-up timer delay of 72ms in PIC? a. CPU resets PIC once again in BOR mode b. BOR reset mode gets disabled c. PIC does not remain in BOR mode until the voltage increases irrespective of stability d. Power-up timer kills 72ms more again
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2) What output is generated by OSC2 pin in PIC oscillator comprising RC components for sychronizing the peripherals with PIC microcontroller? a. (1/2) x frequency of OSC1 b. (1/4) x frequency of OSC1 c. (1/8) x frequency of OSC1 d. (1/16) x frequency of OSC1
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3) Which form of clocking mechanism is highly efficient and reliable for crystal or ceramic clock sources for operating at the range of 5- 200 kHz in PIC? a. RC b. LP (Low-Power Clocking) c. XT d. HS (High Speed)
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4) Which significant feature/s of crystal source contribute/s to its maximum predilection and utility as compared to other clock sources? a. High accuracy b. Proficiency in time generation c. Applicability in real-time operations d. All of the above
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5) What is the executable frequency range of High speed (HS) clocking method by using cystal/ ceramic/ resonator or any other external clock source? a. 0-4 MHz b. 5-200 KHz c. 100kHz- 4 MHZ d. 4-20 MHz
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6) How many bits are required for addressing 2K & 4K program memories of PIC 16C61 respectively? a. 4 & 8 bits b. 8 & 16 bits c. 11 & 12 bits d. 12 & 16 bits
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7) What location is attributed to 'goto Mainline' instruction in the program memory of PIC 16C61? a. 000H b. 004H c. 001H d. 011H
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8) When do the special address 004H get automatically loaded into the program counter? a. After the execution of RESET action in program counter b. After the execution of 'goto Mainline ' instruction in the program memory c. At the occurrence of interrupt into the program counter d. At the clearance of program counter with no value
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9) How many bits are utilized by the instruction of direct addressing mode in order to address the register files in PIC? a. 2 b. 5 c. 7 d. 8
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10) Which registers are adopted by CPU and peripheral modules so as to control and handle the operation of device inhibited in RFS? a. General Purpose Register b. Special Purpose Register c. Special Function Registers d. All of the above
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11) Which among the below specified registors are addressable only from bank1 of RFS? a. PORTA (05H) b. PORTB (06H) c. FSR (04H) d. ADCON0 (07H)
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12) Which register acts as an input-output control as well as data direction register for PORTA in bank 2 of RFS? a. INDF (80H) b. TRISB (85H) c. TRISA (85H) d. PCLATH (8A)
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13) Which bank of RFS has a provision of addressing the status register? a. Only Bank 1 b. Only Bank 2 c. Either Bank 1 or Bank 2 d. Neither Bank 1 nor Bank 2
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14) Where are the prescalar assignments applied with a usage of PSA bit? a. Only RTCC b. Only Watchdog timer c. Either RTCC or Watchdog timer d. Neither RTCC nor Watchdog timer
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15) Where is the exact specified location of an interrupt flag associated with analog-to-digital converter? a. INTCON b. ADCON0 c. ADRES d. PCLATH
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16) Which bit permits to enable (if set) or disable (if cleared) all the interrupts in an INTCON register? a. GIE b. ADIE c. RBIE d. TOIE
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17) When does it become possible for a bit to get accessed from bank '0' in the direct addressing mode of PICs? a. Only when RPO bit is set 'zero' b. Only when RPO bit is set '1' c. Only when RPO bit is utilized along with 7 lower bits of instruction code d. Cannot Predict
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18) When does it become feasible for portB pins (RB4 to RB7) to support its unique feature of 'interrupt on change'? a. By configuring all the pins (RB4-RB7) as inputs b. By configuring all the pins (RB4-RB7) as outputs c. By configuring any one of the pins as inputs d. By configuring any one of the pins as outputs
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19) Which digital operations are performed over the detected mismatch outputs with an intention to generate a single output RB port change output? a. OR b. AND c. EX-OR d. NAND
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20) What is the purpose of acquiring two different bits from INTCON register for performing any interrupt operation in PIC 16C61 / 71? a. One for enabling & one for disabling the interrupt b. One for enabling the interrupt & one for its occurrence detection c. One for setting or clearing the RBIE bit d. None of the above
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