MCQs: In the simulation process, which step specifies the conversion of VHDL intermediate code so that it can be used by the simulator?
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MCQs: Which type of simulator/s neglect/s the intra-cycle state transitions by checking the status of target signals periodically irrespective of any events?
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MCQs: Which among the following is not a characteristic of 'Event-driven Simulator'?
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MCQs: Which among the following is an output generated by synthesis process?
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MCQs: Register transfer level description specifies all of the registers in a design & ______ logic between them.
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MCQs: In synthesis process, the load attribute specify/ies the existing amount of _________load on a particular output signal.
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MCQs: Which attribute in synthesis process specify/ies the resistance by controlling the quantity of current it can source?
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MCQs: Which type of digital systems exhibit the necessity for the existence of at least one feedback path from output to input?
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MCQs: The output of sequential circuit is regarded as a function of time sequence of __________.
A. Inputs
B. Outputs
C. Internal States
D. External States
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MCQs: The time required for an input data to settle _____ the triggering edge of clock is known as 'Setup Time'.
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MCQs: Hold time is defined as the time required for the data to ________ after the triggering edge of clock.
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MCQs: An Antifuse programming technology is predominantly associated with _____.
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MCQs: In fusible link technologies, the undesired fuses are removed by the pulse application of _____voltage & current to device input.
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MCQs: Which programming technology/ies is/are predominantly associated with SPLDs and CPLDs?
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MCQs: Before the commencement of design, the clocking strategy determine/s __________
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MCQs: Which method/s of physical clocking is/are a /the recursive structure where the memory elements are grouped together to make the use of nearby or same distribution points?
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MCQs: Increase in the physical distance of H-tree _________the skew rate.
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MCQs: Which type of MOSFET exhibits no current at zero gate voltage?
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MCQs: In enhancement MOSFET, the magnitude of output current __________ due to an increase in the magnitude of gate potentials.
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MCQs: In DIBL, which among the following is/are regarded as the source/s of leakage?
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