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MCQs: In VLSI design, which process deals with the determination of resistance & capacitance of interconnections?
Category: Electronic Engineering Questions, Published by: T-Code Scripts
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MCQs: Among the VHDL features, which language statements are executed at the same time in parallel flow?
Category: Electronic Engineering Questions, Published by: T-Code Scripts
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MCQs: In Net-list language, the net-list is generated _______synthesizing VHDL code.
Category: Electronic Engineering Questions, Published by: T-Code Scripts
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MCQs: In VHDL, which object/s is/are used to connect entities together for the model formation?
Category: Electronic Engineering Questions, Published by: T-Code Scripts
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MCQs: Which data type in VHDL is non synthesizable & allows the designer to model the objects of dynamic nature?
Category: Electronic Engineering Questions, Published by: T-Code Scripts
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MCQs: Which type of simulation mode is used to check the timing performance of a design?
Category: Electronic Engineering Questions, Published by: T-Code Scripts
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MCQs: In the simulation process, which step specifies the conversion of VHDL intermediate code so that it can be used by the simulator?
Category: Electronic Engineering Questions, Published by: T-Code Scripts
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MCQs: Which type of simulator/s neglect/s the intra-cycle state transitions by checking the status of target signals periodically irrespective of any events?
Category: Electronic Engineering Questions, Published by: T-Code Scripts
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MCQs: Which among the following is not a characteristic of 'Event-driven Simulator'?
Category: Electronic Engineering Questions, Published by: T-Code Scripts
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MCQs: Which among the following is an output generated by synthesis process?
Category: Electronic Engineering Questions, Published by: T-Code Scripts
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MCQs: Register transfer level description specifies all of the registers in a design & ______ logic between them.
Category: Electronic Engineering Questions, Published by: T-Code Scripts
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MCQs: In synthesis process, the load attribute specify/ies the existing amount of _________load on a particular output signal.
Category: Electronic Engineering Questions, Published by: T-Code Scripts
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MCQs: Which attribute in synthesis process specify/ies the resistance by controlling the quantity of current it can source?
Category: Electronic Engineering Questions, Published by: T-Code Scripts
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MCQs: Which type of digital systems exhibit the necessity for the existence of at least one feedback path from output to input?
Category: Electronic Engineering Questions, Published by: T-Code Scripts
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MCQs: The output of sequential circuit is regarded as a function of time sequence of __________.
A. Inputs
B. Outputs
C. Internal States
D. External States
Category: Electronic Engineering Questions, Published by: T-Code Scripts
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MCQs: The time required for an input data to settle _____ the triggering edge of clock is known as 'Setup Time'.
Category: Electronic Engineering Questions, Published by: T-Code Scripts
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MCQs: Hold time is defined as the time required for the data to ________ after the triggering edge of clock.
Category: Electronic Engineering Questions, Published by: T-Code Scripts
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MCQs: An Antifuse programming technology is predominantly associated with _____.
Category: Electronic Engineering Questions, Published by: T-Code Scripts
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MCQs: In fusible link technologies, the undesired fuses are removed by the pulse application of _____voltage & current to device input.
Category: Electronic Engineering Questions, Published by: T-Code Scripts
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MCQs: Which programming technology/ies is/are predominantly associated with SPLDs and CPLDs?
Category: Electronic Engineering Questions, Published by: T-Code Scripts
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